Because of their inherent material properties, gallium arsenide (GaAs) metal semiconductor field effect transistor (MESFET) devices exhibit charge storage effects which manifest themselves as time- and level-dependent hysteresis in circuits that employ MESFETs as amplifying and/or switching elements. Various techniques have been used to overcome or minimize these effects, including autozeroing and cascoding. Autozeroing is very effective, but has the disadvantage of requiring additional circuitry which, in general, precludes such circuits from use in flash analog-to-digital (A/D) converters having on the order of 2.sup.N comparators, where N is the number of bits of resolution.
FIG. 1 illustrates a basic prior art regenerative comparator circuit 10 implemented in silicon bipolar technology, and FIG. 2 shows an analogous GaAs MESFET implementation in circuit 20. Circuits 10 and 20 include inputs V.sub.IN+ and V.sub.IN-, and outputs V.sub.OUT and NV.sub.OUT. In one use of circuits 10 and 20, V.sub.IN+ may receive a reference voltage and V.sub.IN- may receive a voltage that is to be compared to the reference voltage. In one use of circuits 10 and 20 during a regenerative period, V.sub.OUT is in a high state and NV.sub.OUT is in a low state when V.sub.IN+ is greater than V.sub.IN-. Conversely, V.sub.OUT is in a low state and NV.sub.OUT is in a high state when V.sub.IN+ is less than V.sub.IN-.
Circuits 10 and 20 include an outer differential amplifier pair (Q.sub.1, Q.sub.2), a differential inner latching or regenerative pair (Q.sub.3, Q.sub.4), and a third differential amplifier pair (Q.sub.5, Q.sub.6), driven by a clock signal CLK and inverted clock signal NCLK. CLK and NCLK originate from an externally applied strobe clock.
The third differential pair (Q.sub.5, Q.sub.6) provide a path through which current from a current source Q.sub.7 can flow from the emitters of the outer differential amplifier pair (Q.sub.1, Q.sub.2) whenever CLK is in a high state and NCLK is in a low state, and the inner regenerative pair (Q.sub.3, Q.sub.4) whenever CLK is in a low and NCLK is in a high state.
Whenever CLK is high, the outer differential pair (Q.sub.1, Q.sub.2) acts as an amplifier on the voltage difference between inputs V.sub.IN+ and V.sub.IN- setting up a voltage offset at the complementary output terminals V.sub.OUT and NV.sub.OUT and charging the parasitic capacitances C.sub.P and NC.sub.P connected to the collector or drain nodes. When CLK switches low, current is steered to the inner regenerative pair (Q.sub.3, Q.sub.4), thereby beginning the regeneration cycle.
The offset stored on C.sub.P and NC.sub.P serves to unbalance the output voltage of the inner regenerative pair (Q.sub.3, Q.sub.4), and the offset then grows exponentially because of the cross-coupled nature of the inner regenerative pair (Q.sub.3, Q.sub.4). The ultimate magnitude of the output voltage difference between V.sub.OUT and NV.sub.OUT is set by the tail current-I.sub.7 flowing through the collector or drain of Q.sub.7 and the values of the load resistors R.sub.L1, R.sub.L2. When the clock again switches high, the inner regenerative pair (Q.sub.3, Q.sub.4) is disabled and the outer differential pair (Q.sub.1, Q.sub.2) is reactivated, and circuit 10 recovers to its original state, wherein the values of V.sub.OUT and NV.sub.OUT are directly influenced by the values of V.sub.in+ and V.sub.in-. Transistors Q.sub.8 -Q.sub.11, and diodes D.sub.8a-i and D.sub.9a-i provide level-shifting and output drive capability.
FIGS. 3a, 3b, and 3c show typical waveforms for circuits 10 and 20 of FIGS. 1 and 2. FIG. 3a shows the voltage of V.sub.IN+ as it changes with time while V.sub.IN- (the dashed line) is held constant FIG. 3b shows CLK changing from a high state during the amplification period to a low state during the regenerative period, to a high state again during the amplification period. Referring to FIG. 3c, whenever CLK is in a high state, the difference in the values of the outputs V.sub.OUT and NV.sub.OUT is determined by the relative values of V.sub.IN+ and V.sub.IN-, shown here as constant values for clarity only. Whenever CLK is in a state low state and NCLK is in a high state, the difference in the output values changes until a maximum is reached when all of the current is flowing through one of the inner transistors Q.sub.3 or Q. When CLK is changed to a high state again, the outputs rapidly change to new values determined by the values of V.sub.IN+ and V.sub.IN- after CLK changes state.
Silicon transistors are free of anomalous charge storage effects, and any hysteresis resulting from charge stored in the junctions and parasitic capacitances tends to manifest itself at high frequencies. On the other hand, GaAs transistors contain defects and traps in the crystal which exhibit charge storage effects with very long (microsecond to millisecond) time constants.
These charge storage effects manifest themselves as low-frequency, frequency-dependent drain conductance and transconductance within field effect transistors (FETs), leading to long-time constant hysteresis in amplifiers and comparators, and even in logic gates. The presence of hysteresis decreases the ability of the circuit to respond properly to small signals, thus limiting the degree of resolution achievable in comparators and amplifiers.
There is a need, therefore, for techniques that minimize the impact of MESFET charge storage and allow increased resolution and operating speed in comparators and amplifiers. There also is a need for a low-hysteresis high-speed regenerative comparator suitable for use in A/D converters that use large numbers of comparators.